1. Field of the Invention
The present invention relates to a device for driving capacitive light emitting elements.
2. Description of the Related Art
Display panels that include capacitive light emitting elements are often called capacitive display panels and marketed as wall-mounted TVs. Typical wall-mounted TVs are plasma display panels (hereinafter called ‘PDP’) and electroluminescence display panels (hereinafter called ‘ELDP’).
FIG. 1 of the attached drawings shows part of a driver device that drives a capacitive display panel to emit light by applying a variety of drive pulses to the capacitive display panel. This driver device is disclosed in Japanese Patent Kokai (Laid-Open Application) No. 2002-156941.
In FIG. 1, a PDP 10 has a plurality of row electrodes (not shown) and a plurality of column electrodes Z1 to Zm arranged to intersect one another. Discharge cells (not shown), which correspond with pixels, are formed at the points of intersection between the row and column electrodes.
A column electrode driver circuit 20 includes a power supply circuit 21, which generates a resonance pulse supply voltage in accordance with switching signals SW1 to SW3, and a pixel data pulse generation circuit 22, which generates a pixel data pulse applied to each of the column electrodes Z1 to Zm on the basis of the resonance pulse supply voltage.
The pixel data pulse generation circuit 22 includes switching elements SWZ1 to SWZm and SWZ10 to SWZm0. The switching elements SWZ1 to SWZm and SWZ10 to SWZm0 are each controlled to become an ON state or an OFF state (turned on or off) individually in accordance with one display line's worth of (m) pixel data bits DB1 to DBm that designate the states (lit or unlit) of the discharge cells on the basis of an inputted picture signal. Each of the switching elements SWZ1 to SWZm enters the ON state as long as the pixel data bit DBi supplied thereto is logic level 1, for example, and applies the resonance pulse supply voltage of the supply line 2 to the corresponding column electrode Zi (Z1 to Zm). On the other hand, when the pixel data bit DBi is logic level 0, the switching element SWZi0 (SWZ10 to SWZm0) enters the ON state and applies the ground potential to the corresponding column electrode Zi (Z1 to Zm). That is, when a resonance pulse supply voltage is applied to the column electrode Zi, a high-voltage pixel data pulse is generated and supplied to the column electrode Zi, and when the ground potential is applied to the column electrode Zi, a low-voltage pixel data pulse is generated and supplied to the column electrode Zi.
The operation of the power supply circuit 21 for generating this resonance pulse supply voltage will be described below.
Switching signals SW1 to SW3 which repeatedly set the switching elements S1 to S3 to the ON state in the order of the switching elements S1, S3, and then S2, are supplied to operate the power supply circuit 21.
When only the switching element S1 enters the ON state in accordance with the switching signal SW1, the capacitor C1 is discharged and the discharge current thereof is released to the power supply line 2 via the coil L1 and diode D1. If the switching element SWZi of the pixel data pulse generation circuit 22 is in the ON state, the discharge current flows into the column electrode Zi of the PDP 10 via the switching element SWZi, the load capacitor C0 that is parasitic on the column electrode Zi is charged, and an accumulation of electrical charge occurs within the load capacitor C0. Therefore, the potential of the power supply line 2 gradually rises because of the resonance action caused by the coil L1 and the load capacitor C0. This voltage increase is the rising edge of the high-voltage pixel data pulse.
When the switching element S3 alone enters the ON state in response to the switching signal SW3, a power supply voltage Va generated by a DC power supply B1 is applied to the power supply line 2. The power supply voltage Va is the maximum voltage of the high-voltage pixel data pulse.
When the switching element S2 alone enters the ON state in response to the switching signal SW2, the load capacitor C0 that is parasitic on the column electrode Zi of the PDP 10 is discharged. The discharge current flows into the capacitor C1 via the column electrode Zi, the switching element SWZi, the power supply line 2, the coil L2, the diode D2, and the switching element S2, whereby the capacitor C1 is charged. That is, the electrical charge that has accumulated in the load capacitor C0 of the PDP 10 is gradually recovered by the capacitor C1 provided in the power supply circuit 21. The voltage of the power supply line 2 gradually drops in accordance with the time constant that is determined by the coil L2 and load capacitor C0. This decrease of the voltage is the trailing edge of the high-voltage pixel data pulse.
That is, in the power supply circuit 21, the electrical charge that has accumulated in the PDP 10 as a capacitive load is recovered by the capacitor C1 and reused, whereby a reduced consumption of electrical power is achieved.
When the switching element SWZ1enters the ON state in response to the pixel data bit DB1 of logic level 1, for example, the resonance pulse supply voltage, whose variation between the leading and trailing edges thereof is gradual and whose maximum voltage is Va, is supplied to the column electrode Z1 as a high-voltage pixel data pulse. On the other hand, when the pixel data bit DB1 is logic level 0, the switching element SWZ10 enters the ON state, and therefore a low-voltage (ground potential) pixel data pulse is applied to the column electrode Z1. Part of the electrical charge that has accumulated in the load capacitor C0 of the PDP 10 is consumed via the current path including the column electrode Z1 and switching element SWZ10. Therefore, if the bit data train for the display lines of the pixel data bit DB1 is successively logic level 1 such as ‘1,1,1, . . . , 1,1,1’, the switching element SWZ1 is fixed in the ON state and the SWZ10 in the OFF state during this interval. As a result, all the electrical charge that has accumulated in the load capacitor C0 of the PDP 10 is not recovered by the capacitor C1. Thus, the resonance pulse supply voltage applied to the power supply line 2 maintains the maximum voltage Va but the resonance amplitude gradually decreases. This is equal to applying a DC power supply voltage to the power supply line 2 (DC drive state).
Accordingly, when a certain type of image should be displayed, a resonance circuit that includes the capacitor C1, coils L1 and L2 and the load capacitor C0 of the PDP 10 enters the DC drive state and this creates the risk of a faulty operation due to the localized generation of heat, noise generation, and so forth.